Semiconductor memories, which are key components of any electronic device1, can be classified either into random access memories (RAM) or read-only memories (ROM)2, as shown in FIG. 1 for example.
In random access memories (RAMs), information can be written or read from any cells multiple times2. Random access memories (RAMs) can be further classified based on the retention of the stored information, into volatile memories (Dynamic RAMs (DRAMs) and static RAMs (SRAMs)) and nonvolatile memories2.
Dynamic RAMs (DRAMs) have been a technology of choice for the past four decades3. Nowadays semiconductor memories represent 21% of the total semiconductor market, and although a large variety of memory types is available, the market is dominated mainly by dynamic RAMs (DRAMs), which make up 48% of the memory market, as shown in FIG. 21. However, dynamic RAMs (DRAMs) have gradually reached their physical scalability limit and data retention time is limited by leakage of the capacitor and the transistor. Another drawback is related to poor energy efficiency, as 40% of the overall power consumption is originated from the system memory power, i.e. DRAM power, and the disk power. Also, high density dynamic RAM technologies have reached its miniaturization limit with lateral feature size of DRAMs memories shrunk down to about 14 nm2.
Emerging contenders for DRAMs seek to address the above concerns, by being non-volatile and scalable to smaller dimensions, for example by using ferroelectric tunnel junction memory (FTJ)4.
A ferroelectric tunnel junction memory consists of two metal electrodes separated by a nanometer-thick ferroelectric layer.4 The tunneling electroresistance effect (TER) occurring in this semiconductor memory predominantly relies on the modulation of the electrostatic potential profile by polarization reversal of an ultrathin ferroelectric barrier, which produces two different electrical resistance states in the ferroelectric tunnel junction, which can be codified as “ON” and “OFF” in a binary code. The use of the tunneling electroresistance effect in a semiconductor memory brings a number of advantages such as for example: i) high fatigue resistance (endurance ˜106 cycles), ii) high speed (“ON/OFF” states can be written with pulses down to 10 ns), iii) high scalability, and iv) simple architecture4,5.
A key challenge to overcome in a ferroelectric tunnel junction memory is to find an adequate material which, in ultrathin film form, i.e. with a thickness below about 4 nm, presents ferroelectric properties. In addition, this ferroelectric material should present synthesis parameters compatible with complementary metal oxide semiconductor processes (CMOS)4, in terms in particular of chemical compatibility and crystallization temperature. Current ferroelectric tunnel junction devices are based on perovskite ferroelectric barriers6, which suffer from lack of CMOS compatibility due to poor interfacing with silicon, an elevated crystallization temperature, and electrical degradation under forming gas treatment. These issues, along with the inability to further scale down, prevent their use in high density memories78.
There is still a need in the art for ferroelectric tunnel junctions and a method of fabrication thereof.
The present description refers to a number of documents, the content of which is herein incorporated by reference in their entirety.